Fan's Website

Hey, this is Fan Zhang, a Ph.D candidate with Department of Electrical and Computer Engineering, Johns Hopkins University advised by Prof. Deliang Fan.

Study on ReRam, In-memory computing, and software/hardware co-design fields. I have authored and co-authored research papers in top-tier EDA conferences including, DAC, DATE, ICCAD, ASP-DAC, ESSCIRC, etc

My main research interests and publications cover the following topics:

In-Memory Computing Based on Volatile & Non-Volatile Memories
Accelerator Design for Deep Neural Networks, Bioinformatics, Graph Processing, etc.
Low Power and Area-efficient In-Sensor Computing for IoT
Approximate Computing
Low power VLSI circuits

news

Apr 22, 2024	Congrats! My paper have been accepted by JSSC! 🥳
Feb 13, 2024	My two papers have been accepted by DAC 2024 and one paper has been accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)!
Aug 17, 2023	I transferred to Johns Hopkins University to finish my PHD (expected to graduate in 2024 Summer).
May 21, 2023	I started another internship at Google TPU group as hardware engineer intern.
Jan 9, 2023	I started my Spring internship at Ansys as Semiconductor R&D intern.

latest posts

Dec 25, 2023	Socks proxy over V2ray
Oct 27, 2023	Docker Insufficient shared memory (shm) Error
Oct 10, 2023	Nvidia Pytorch Usage

selected publications

2024

JSSC

A 65nm RRAM Compute-in-Memory Macro for Genome Processing

Fan Zhang, Amitesh Sridharan, Wangxin He, and 7 more authors

In 2024 IEEE Journal of Solid State Circuits (JSSC), 2024

Bib PDF

@inproceedings{JSSC_24,
  author = {Zhang, Fan and Sridharan, Amitesh and He, Wangxin and Yeo, Injune and Liehr, Maximilian and Zhang, Wei and Cady, Nathaniel and Cao, Yu and Seo, Jae-sun and Fan, Deliang},
  booktitle = {2024 IEEE Journal of Solid State Circuits (JSSC)},
  title = {A 65nm RRAM Compute-in-Memory Macro for Genome Processing},
  year = {2024},
  volume = {},
  number = {},
  doi = {},
}

2023

IEEE JETCAS

Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read Alignment

Fan Zhang, Shaahin Angizi, Jiao Sun, and 2 more authors

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023

Bib PDF

@article{10034770,
  author = {Zhang, Fan and Angizi, Shaahin and Sun, Jiao and Zhang, Wei and Fan, Deliang},
  journal = {IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
  title = {Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read Alignment},
  year = {2023},
  volume = {13},
  number = {1},
  pages = {332-343},
  doi = {10.1109/JETCAS.2023.3241545},
}

2022

DAC
XMA: A Crossbar-Aware Multi-Task Adaption Framework via Shift-Based Mask Learning Method

Fan Zhang, Li Yang, Jian Meng, and 3 more authors

In Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022

Abs Bib PDF

ReRAM crossbar array as a high-parallel fast and energy-efficient structure attracts much attention, especially on the acceleration of Deep Neural Network (DNN) inference on one specific task. However, due to the high energy consumption of weight re-programming and the ReRAM cells’ low endurance problem, adapting the crossbar array for multiple tasks has not been well explored. In this paper, we propose XMA, a novel crossbar-aware shift-based mask learning method for multiple task adaption in the ReRAM crossbar DNN accelerator for the first time. XMA leverages the popular mask-based learning algorithm’s benefit to mitigate catastrophic forgetting and learn a task-specific, crossbar column-wise, and shift-based multi-level mask, rather than the most commonly used element-wise binary mask, for each new task based on a frozen backbone model. With our crossbar-aware design innovation, the required masking operation to adapt for a new task could be implemented in an existing crossbar-based convolution engine with minimal hardware/memory overhead and, more importantly, no need for power-hungry cell re-programming, unlike prior works. The extensive experimental results show that, compared with state-of-the-art multiple task adaption Piggyback method [1], XMA achieves 3.19% higher accuracy on average, while saving 96.6% memory overhead. Moreover, by eliminating cell re-programming, XMA achieves 4.3x higher energy efficiency than Piggyback.
@inproceedings{10.1145/3489517.3530458, author = {Zhang, Fan and Yang, Li and Meng, Jian and Seo, Jae-sun and Cao, Yu (Kevin) and Fan, Deliang}, title = {XMA: A Crossbar-Aware Multi-Task Adaption Framework via Shift-Based Mask Learning Method}, year = {2022}, isbn = {9781450391429}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3489517.3530458}, doi = {10.1145/3489517.3530458}, booktitle = {Proceedings of the 59th ACM/IEEE Design Automation Conference}, pages = {271–276}, numpages = {6}, keywords = {neural networks, in-memory computing, multi-task learning}, location = {San Francisco, California}, series = {DAC '22}, }

2021

DAC

Max-PIM: Fast and Efficient Max/Min Searching in DRAM

Fan Zhang, Shaahin Angizi, and Deliang Fan

In 2021 58th ACM/IEEE Design Automation Conference (DAC), 2021

Bib PDF

@inproceedings{9586096,
  author = {Zhang, Fan and Angizi, Shaahin and Fan, Deliang},
  booktitle = {2021 58th ACM/IEEE Design Automation Conference (DAC)},
  title = {Max-PIM: Fast and Efficient Max/Min Searching in DRAM},
  year = {2021},
  volume = {},
  number = {},
  pages = {211-216},
  doi = {10.1109/DAC18074.2021.9586096},
}

2020

JETC
Mitigate Parasitic Resistance in Resistive Crossbar-Based Convolutional Neural Networks

Fan Zhang, and Miao Hu

J. Emerg. Technol. Comput. Syst., May 2020

Abs Bib PDF

Traditional computing hardware often encounters on-chip memory bottleneck on large-scale Convolution Neural Networks (CNN) applications. With its unique in-memory computing feature, resistive crossbar-based computing attracts researchers’ attention as a promising solution to the memory bottleneck issue in von Neumann architectures. However, the parasitic resistances in crossbar deviate its behavior from the ideal weighted summation operation. In large-scale implementations, the impact of parasitic resistances must be carefully considered and mitigated to ensure circuits’ functionality. In this work, we implemented and simulated CNNs on resistive crossbar circuits with consideration of parasitic resistances. Moreover, we carried out a new mapping scheme for high utilization of crossbar arrays on convolution, and a mitigation algorithm to mitigate parasitic resistances in CNN applications. The mitigation algorithm considers parasitic resistances as well as data/kernel patterns of each layer to minimize the computing error in crossbar-based convolutions of CNNs. We demonstrated the proposed methods with implementations of a 4-layer CNN on MNIST, and residual neural network (ResNet) (20, 32, and 56) on CIFAR-10. Simulation results show the proposed methods well mitigate the parasitic resistances in crossbars. With our methods, modern CNNs on crossbars can preserve ideal (software) level classification accuracy with 6-bit ADCs and DACs implementation.
@article{10.1145/3371277, author = {Zhang, Fan and Hu, Miao}, title = {Mitigate Parasitic Resistance in Resistive Crossbar-Based Convolutional Neural Networks}, year = {2020}, issue_date = {July 2020}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, volume = {16}, number = {3}, issn = {1550-4832}, url = {https://doi.org/10.1145/3371277}, doi = {10.1145/3371277}, journal = {J. Emerg. Technol. Comput. Syst.}, month = may, articleno = {25}, numpages = {20}, keywords = {Resistive crossbar, convolutional neural network, parasitic resistance}, }